Field
Embodiments described herein generally relate to managing power consumption of a device.
Background
Leakage power is a significant contributor to overall energy consumption in a computing system. In some computing systems reducing leakage power during active times is accomplished by power-gating components within a core of the computing system. Power-gating is a technique that reduces stand-by or leakage power by transitioning a computing system (or individual components of a computing system such as a core and its associated caches) from an active state to a sleep state. In a sleep state, substantially all components of the computing system that are power-gated are powered-down. However, leakage power is also a significant issue when a computer system's processor is idle or halted but not power-gated. The leakage power consumption drops to negligible levels when the processor enters a full-sleep state in which the cores and caches of the computing system are also power-gated.
Power-gating cores and caches is a common technique in current processors. Many applications, both in client and server spaces, have significant idle times during which power-gating can be invoked. These include interactive and I/O-intensive applications. However, optimal power-gating is difficult to achieve. Transitioning between active and full sleep states requires time and energy to flush the caches of the system and move the architectural state of the system into and out of cores. As a result, time and power are consumed while the program makes no forward progress. Entering a full sleep state incurs a performance and energy overhead. Hence, it is desirable that a computing system be in a sleep state for a sufficient amount of time to compensate for the cost. If a computing system is not in a sleep state for a sufficient amount of time, total power can actually increase and negatively impact the computing system. Thus, an ineffective power-gating scheme can sacrifice both performance and energy-consumption of the computing system.